| 摘要 |
PURPOSE:To realize the mixing and multiplexing of data at differnet speed, by selecting the combination of speed of multiplex data dynamically. CONSTITUTION:A fixed address (d) is allocated to each channel. A channel address (u) changes periodically according to a counter 9 and flip-flops 12 and 13, and the channel detecting the fact that its own address is designated by a comparator 2 opens a gate 1, and sends a bit of channel mounting information (a) and channel speed information (b) and (c) to a multiplexing circuit. The channel detecting the fact that its own channel is designated by a comparator 3 opens a gate 4, and sends an envelope (e) of eight bits to the multiplexing circuit. In a shift register 5, the allocation information of a time slot is held, and in shift registers 6 and 7, speed information for detecting speed address are held. The fetching of the channel speed information in the shift registers 6 and 7 can be controlled by controlling a separator 8.
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