| 摘要 |
<p>A phase detection circuit for detecting the difference in phase between an analog signal including clock components, and a reference clock signal, is described. It includes an analogto-digital converter for sampling the analog signal at the frequency of the reference clock signal and providing a k-bit first digital signal. It also includes a delay circuit for sampling the first digital signal at a frequency equal to one half the frequency of the reference clock signal and providing a k-bit second digital signal. Finally, a multiplier is included for multiplying the first digital signal by the second digital signals to provide data representative of the phase difference. The circuit of the invention is capable of operating at a processing speed which is twice as high as the modulation rate of analog signals.</p> |
