发明名称 SEMICONDUCTOR MEMORY CIRCUIT
摘要 PURPOSE:To reduce the power consumption of an unselected column, by switching FETs inserted in series in the power soruce lines of all columns of an S-RAM with a column decoder. CONSTITUTION:The FET6 for power down is inserted into the power source line 5 for a memory cell, a sense amplifier, and a R/W controller at every column, and a column selection signal from the column decoder 4 is applied on the gate electrode of the FET6. Only the FET on a selected column is turned ON, and a sufficient power is supplied to the memory cell, the sense amplifier and the R/W controller. Meanwhile, the FET6 on the unselected column goes to an OFF state, and the power source is disconnected. However, power consumption is limited to a minimum level to prevent the storage of the memory cell from being lost even when the power source is disconnected.
申请公布号 JPS63241789(A) 申请公布日期 1988.10.07
申请号 JP19870074212 申请日期 1987.03.30
申请人 AGENCY OF IND SCIENCE & TECHNOL 发明人 KOBAYASHI NAOKI
分类号 G11C11/401;G11C11/34;G11C11/407;G11C11/41;G11C11/413 主分类号 G11C11/401
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