| 摘要 |
PURPOSE:To reduce load on a CPU and to accelerate processing speed, by performing data transfer on a path where data is transferred from a memory cell array to a transfer register and to the memory cell array in a transfer mode. CONSTITUTION:When the data transfer is performed in the inside of a main memory without inputerosing the CPU, a transfer mode instruction input from the CPU becomes active for a constant time in a first RAS cycle I. At this time, the content of the memory cell array 1 at an address designated by an address input is read out, and is transferred to a transfer register 12 via a multiplexer 13. Next, in a second RAS cycle II, the signal input of the inverse of WE from the CPU becomes active for the constant time, and a transfer mode designation capacity becomes active. At this time, the content of the memory cell array 1 at the address designated by the address input is transferred via the multiplexer 13. By repeating such operation corresponding to the data transfer, it is possible to perform the data transfer between the memories without interposing the CPU.
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