| 摘要 |
PURPOSE:To reduce the area of a transistor forming region by forming structure in which a source region, a region including a channel and a drain region are arranged vertically to the surface of a substrate. CONSTITUTION:Capacitance consisting of a cell plate 1, an oxide film 4 and an N-type impurity diffusion layer 3 is shaped onto the sidewall of a trench cut to a P-type Si substrate 2. An Si epitaxial layer is grown selectively in a region including a section exposed to an Si surface in a substrate-side electrode in the capacitance, and a source region 7, a layer 10 containing a channel 8 and a drain region 9 are formed in the direction vertical to the surface of the substrate in the epitaxial layer. A high-concentration P-type diffusion region 11 is shaped to the base of the trench in order to prevent the leakage of an N-type diffusion region 3 in an adjacent cell. Accordingly, an area required for forming a transistor can be reduced, the area of a memory cell is also diminished largely, and excellent transistor characteristics generating no short channel effect can be acquired. |
