| 摘要 |
PURPOSE:To simply constitute a data transmission buffer circuit of a node for time division multiplex transmission by using a buffer comprising a RAM alternately and generating a write pointer and a read pointer. CONSTITUTION:A dataway transmission section A and an external device transmission section B constitute a data transmission buffer circuit in one node. FIFO buffer circuits 1, 2, 3, 4 consist of a RAM. The write/read of the circuits 1, 2 is executed by using a changeover circuit 13 at each transmission period to connect a write pointer generating section 11 or a read pointer generating section 12 to the buffer 1 or 2. The write/read of the circuits 3, 4 is conducted in parallel with the changeover of the circuits 1, 2. Thus, the data transmission buffer circuit of the node to apply time division multiplex transmission is constituted simply.
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