| 摘要 |
PURPOSE:To attain the interface of a video signal without using a frame memory by compressing the pulse duration of a horizontal synchronizing signal when the transfer speed of the dot clocks of a video signal generating side and a display device side is different. CONSTITUTION:Video data VDATA synchronizes with the dot clock (DCK) 1 and shifted in a first shift register SR1. At the time of shifting in for one horizontal period, the output 12 of the SR 1 is inputted to a second shift register SR 2 in parallel according to the horizontal synchronizing signal Hsyc from a video signal generating side. At this time, in the signal Hsyc, the pulse duration is compressed in a pulse duration transforming circuit 3, a load signal 10 is generated to make the terminal L of the SR 2 active. When the contents of the SR 1 are inputted in parallel, the DCK 2 synchronizing with display data 11 is generated in a DCK generating circuit 4 to make the clock terminal C of the SR 2 active. Then, the contents of the SR 1 inputted in parallel are sequentially read as the display data 11, fed to a liquid crystal display module 6 and displayed.
|
