| 摘要 |
PURPOSE:To prevent a read-out level voltage amplitude from dropping due to a noise between a pair of adjacent bit lines by a capacity between bits, by dividing a memory cell train into blocks by the crossing of a pair of bit lines, and arranging alternately the block connected with a cell to bit lines at every other line, and the block connected with the cell to the bit lines at every two other lines. CONSTITUTION:In areas (a), (c), a memory cell is connected alternately at every other bit line, and in areas (b), (d), the memory cell is connected to every two other bit lines. At the time of selecting a dummy word line, DWL1 to WL0, DWL0 to WL0', and DWL1 to WL1, DWL0 to WL1', and DWL0 to WL2, DWL1 to WL2', and WWL0 to WL3, DWL1 to WL3' are selected in the area (a), the area (b), the area (c), and the area (d), respectively. According to this constitution it does not occur that the read-out voltage amplitude drops due to a noise between a pair of bit lines by the capacity between the bit lines, a memory cell train to which a usual dummy cell method can be applied can be realized, and a memory device having high reliability is obtained.
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