| 摘要 |
<p>A semiconductor memory device provided with improved redundant scheme is disclosed. The memory device comprises a plurality of sub-arrays each having a plurality of normal segment word lines and at least one redundant segment word line arranged in rows common with other sub-arrays, a plurality of control normal word lines in the rows extending through the plurality of sub-arrays, at least one control redundant word line extending in the row through the sub-arrays, a plurality of first block control lines and second block control lines, each first and second block control lines being provided for each sub-array, a plurality of first selecting means each coupled to one of the control normal word lines the one of the first block control line and one of the normal segment word lines for selecting the one normal segment word lines in response to the selection levels of the one control normal word line and the one first block control line, a plurality of second selecting means coupled to the control redundant word line, one of the second block control lines and the one redundant segment word line, a plurality of normal decoders provided for the control normal words lines, at least one redundant decoder provided for the control redundant word line, means for selecting one of the first block control lines when the at least one control redundant word line is not selected, means for making all the first block control lines at the non-selection level when the at least one control redundant word line is selected, and means for selecting one of the second block control lines upon the selection of the control redundant word line.</p> |
