A method of combining gate array and standard cell circuits on a common semiconductor chip.

摘要

A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells (22, 58) and gate array cells (54, 56), on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries (18) and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type (22, 58) or gate array type circuits (54, 56) are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.