发明名称 FREQUENCY MULTIPLICATION CIRCUIT
摘要 PURPOSE:To prevent an influence due to the fluctuation of a parameter by forming an oscillation circuit which has a sufficiently larger frequency than the frequency of an input signal, and presuming the half of a period, during which the input signal is inputted, by using a counter and a 1/2 latch. CONSTITUTION:A CR oscillator 1 is designed beforehand so as to oscillate at the sufficiently larger frequency f2 than the frequency f1 of the input signal from a terminal 2, and when the input signal pulse is L, the output pulse of the oscillator 1 at the time when the input pulse is H is counted by the counter 5 which is reset through a delay circuit 6. Then, according to the signal of an invertor 7, the value of the counter 5 till the trailing edge of the input signal is shifted by one bit and is latched as the half value by the 1/2 latch 9. Then, the output signal of the circuit 1 is counted from the trailing edge of the input signal until it coincides with the output of the latch 9, and a coincidence signal is outputted.
申请公布号 JPS63232708(A) 申请公布日期 1988.09.28
申请号 JP19870066140 申请日期 1987.03.20
申请人 NEC CORP 发明人 SUGIYAMA TAKAHIRO
分类号 H03K5/00 主分类号 H03K5/00
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