| 摘要 |
<p>PURPOSE:To detect the abnormality of synchronization within one period by deciding synchronizing and asynchronizing states by the pattern between the state of a counter and the synchronizing signal train in one cycle from a shift register. CONSTITUTION:The shift register 3 is set by one shorter than the cycle of the synchronizing signal Ss and stores one period of the synchronizing signal Ss by receiving a clock T and the synchronizing signal Ss. The state of the counter 1 and that of the shift register 3 are inputted in a synchronization deciding circuit 4 and in the case of asynchronous state the synchronization deciding circuit 4 outputs one output, for example, then a flip flop 5 controls a selector 2 in order to make the counter 1 in a specified action state by the synchronizing signal Ss. Thus, the abnormality of synchronization can be directly detected and the error of data to the error of synchronization can be removed.</p> |
