| 摘要 |
PURPOSE:To prevent leaking of memory cell data, by setting the concentration of impurities in the vicinity of the channel of a parasitic MOS transistor to be higher than that in the channel region of a MOS transistor. CONSTITUTION:After an N<+> type embedded layer 2 is formed on the surface of a P-type Si substrate 1, a P<-> type Si epitaxial layer 3, an Si3N4 layer 21 and an insulating layer 4 are sequentially formed. Then, a trench, whose depth reaches the inside of the embedded layer 2, is formed, and an insulating layer 6 is formed. Then the insulating layer 6 is selectively removed, and an N<+> poly Si layer is formed. Counter electrodes 7 are made to remain and formed on the side wall surface of the trench 5. Then the surfaces of the counter electrodes 7 are oxidized. Thereafter a dielectric layer 8 is formed. An N<+> poly Si layer is grown, and a storage electrode 9 is formed. Then, the dielectric layer 8 and the layer 21 are removed. After a region 10 is formed, an insulating layer 11 is formed. Then word lines 12A and 12B and the like are formed. After the surface is covered with an insulating layer 13, regions 14A, 14B and 14C are formed. After the regions 14A, 14B and 14C are exposed, a titanium layer is formed, and conductor layers 15A and 15B are formed. An interlayer insulating layer 16 is deposited. An Al bit line 18 is formed. Thus a holding characteristic as a memory is enhanced, and decrease in life of a capacitor can be prevented. |
