发明名称 COMBINATIONAL LOGIC CIRCUIT
摘要 PURPOSE:To decrease the number of wirings for going to a coding area, and to realize a high integration of a combinational logic circuit by using two input logic circuits continued and arranged in the combinational logic circuit, and setting a connecting point of each input of one of the adjacent two input logic circuits, as an input. CONSTITUTION:Two input NAND circuits 1-16 of a decoder use combinational logic circuit are continued and arranged, and each input of one of the adjacent NAND circuits 1-16 is continued and connected. Also, wirings 21-29 and 41-48 from this connecting point are connected to address signal lines in coding areas A, B, respectively. In this case, when one piece in areas A1-A4 becomes active, and simultaneously, one piece in area B1-B4 becomes active, one of the NAND circuits 1-16 is selected, becomes active and outputted, and number of wirings for going to the areas A, B is decreased, and a high integration of the combinational logic circuit can be realized.
申请公布号 JPS63227125(A) 申请公布日期 1988.09.21
申请号 JP19870061514 申请日期 1987.03.17
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMADA TOSHIRO
分类号 G06F7/00;H03M7/00 主分类号 G06F7/00
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