| 摘要 |
PURPOSE:To reduce a dead space on a chip to a minimum when a reference- voltage circuit is not required and to enhance the element utilization efficiency by a method wherein transistor arrays composed of a number of transistors are arranged in rows and transistors, whose emitter area is big and whose pair characteristics are excellent, are installed on one side. CONSTITUTION:Transistor arrays 2 composed of a number of transistors are arranged in rows; transistors 6-10 whose emitter area is big and whose pair characteristics are excellent are installed on one side. For example, said transistors 6-10 with the excellent pair characteristics are used as transistor for a reference voltage use and are wired and corrected to a part of the transistor arrays 2 so that a reference-voltage circuit is constituted. By this setup, when, e.g., a circuit requiring no reference voltage is to be constituted, it is possible to reduce a dead space to a minimum and to enhance the element utilization efficiency. In addition, if the transistors with the excellent pair characteristics and the transistor arrays are wired by, e.g., aluminum, polysilicon or the like, it is possible to constitute the reference-voltage circuit. |
