发明名称 VECTOR INSTRUCTION TRANSMISSION CONTROL SYSTEM
摘要 PURPOSE:To improve a processing capability at the time of changing a vector length by providing a logic circuit for turning a vector length changing flag 'on' for every stage of the respective instruction managing pipe lines of an instruction managing part and a circuit for referring to the vector length changing flag and checking a register interference. CONSTITUTION:The logic circuit for turning the vector length changing flag 64C 'on' for every stage of the respective instructin managing pipe lines of the instruction managing part and the circuit 63 for referring to the vector length changing flag and checking the register interference are provided. The interference of a vector instruction with the register is only checked immediately after all the vector instructions and the flag preceding to the 'on' of the vector length changing flag are turned 'on' and the transmission of the vector instruction is controlled based on the register interference check result. Thereby, the transmission of a succeeding instruction especially at the time changing from a large vector length to a small vector length is made faster and a processing capability at the time of changing the vector length of vector data processor is improved.
申请公布号 JPS63225865(A) 申请公布日期 1988.09.20
申请号 JP19870059470 申请日期 1987.03.13
申请人 FUJITSU LTD 发明人 HASEGAWA JUNKO;SAKAMOTO KAZUSHI
分类号 G06F17/16;G06F15/78 主分类号 G06F17/16
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