| 摘要 |
PURPOSE:To attain serial/parallel conversion for an auxiliary data signal or the like in a transmission line system by providing a frequency division circuit whose reset pulse is formed by a clock synchronously with a parallel data. CONSTITUTION:A 1/n frequency divider circuit 8 whose reset pulse is formed by a clock having a frequency f/n includes a reset pulse formed by a frequency division clock synchronously with a parallel data. Then n-kind of parallel data sent from a serial/parallel conversion circuit 1 is inserted into an auxiliary data bit 7 in the frame format of a period of 1/f[sec] in the data processing system 3-1. Then n-kind of auxiliary data signals and a clock signal having the period of f/n[sec] are sent in the data processing system 3-2. The clock having the period of f/n[sec] is multiplied by (n) by a multiplier circuit 11, thereby being an output clock. Then the n-phase clock given to a parallel/serial convertion circuit 2 is realized by using the reset pulse formed by the clock having the period of f/n to initialize the 1/n frequency division circuit 8 so that the phase of the n-phase clock is synchronized with both phases of the n-kind of data and the output clock. |
