| 摘要 |
PURPOSE:To perform the design of a P-N-P transistor clamping type memory cells suitable for high capacity, high speed reading definitely, by providing specified relationship among the lower limit of an emitter grounded current amplification factor, the base length, and the base impurity concentration of a clamping parasitic P-N-P transistor. CONSTITUTION:A base and a collector are connected in a crossed manner in N-P-N driving transistors Q1 and Q2. Clamping parasitic P-N-P transistors Q3 and Q4 are provided for the collectors of Q1 and Q2. A semiconductor memory device has memory cells including said transistors Q1-Q4. Specified relationship is provided among the lower limit of the emitter grounded amplification factor hFE of said P-N-P transistors Q3 and Q4, the base length L, the emitter length W, and the base region impurity concentration ND, which are the device constants of the P-N-P transistors Q3 and Q4. Namely, an expression qnio<2>DELTA.W. Dpea/ND.L.IR>=1/[hFE(Q1)-0.35/IR.R2] is satisifed. |
