READ-ONLY MEMORY FOR A GATE ARRAY ARRANGEMENT

摘要

The construction of a read-only memory involves basic cells (GZ) consisting of at least three P-channel transistors (TP) and three N-channel transistors (TN). Data is stored by using only the outer transistors (TP1, TP2 or TN1, TN2), whilst the inner transistors are not used. The storage of data is determined by the connection or non-connection of the gate electrode (G) of a transistor (TP, TN) with a word line (W), the drain electrode with a bit line and the source electrode with fixed supply potential (VDD, VSS). The layout of the basic cell (GZ) is such that gate connections are made in the inner part of the basic cell and the word lines (W) and bit lines (B) extend towards each other vertically via the basic cell. Read-only memories of the size required may be produced by arranging basic cells of this type in vertical and horizontal rows.