发明名称 FREMGANGSMAADE OG APPARAT TIL OVERFOERING AF ADRESSER
摘要 An address path which transfers addresses from a number of sources includes an incrementing circuit. The address includes a plurality of address bits and integrity bits. The address bits are applied to the incrementing circuit while the integrity bits are applied in parallel to a programmable logic device (PLD). While the address is being transferred or incremented as required, the PLD independently generates a number of transform bits defining a characteristic of the number of address bits predicted to change state. Thereafter, the transform bits are used to transform the address integrity bits for transfer with the incremented address. The incremented address, transform bits and integrity bits are logically combined for verifying that the address was transferred and/or incremented without error.
申请公布号 DK497988(A) 申请公布日期 1988.09.07
申请号 DK19880004979 申请日期 1988.09.07
申请人 HONEYWELL BULL INC. 发明人 BARLOW, GEORGE J.;KEELEY, JAMES W.;NIBBY, CHESTER M. JR.
分类号 G06F11/10;G06F12/08;G06F12/10;G06F12/16;(IPC1-7):G06F11/10 主分类号 G06F11/10
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