发明名称 MUTE CIRCUIT
摘要 PURPOSE:To prevent muting from being conducted due to a voice during communication by applying muting for a prescribed time only from the point of time of high frequency signal arrival in an FSK receiver. CONSTITUTION:A delay signal (g) goes to an H level while a high frequency signal is being received, resulting that a mute control signal (h) outputted from an AND circuit 19 goes to an H level while a data signal is received after an MPU 17 detects a bit synchronizing signal, the mute switch 12 is opened to apply muting. On the other hand, when the reception of a data signal is finished and the audio signal is received, since a noise squelch control signal (e) and a mute control signal (h) go both to an L level, the mute switches 11, 12 are both closed and the muting is released. As a result, even when a signal similar to the bit synchronizing signal is generated during communication, it is not intermitted.
申请公布号 JPS63206025(A) 申请公布日期 1988.08.25
申请号 JP19870037808 申请日期 1987.02.23
申请人 FUJITSU TEN LTD 发明人 MAEDA KEIICHI
分类号 H04B1/10;H04B7/26 主分类号 H04B1/10
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