发明名称 LOAD PULSE GENERATING CIRCUIT
摘要 PURPOSE:To attain accurate coding/decoding by using a retiming control pulse from a load pulse retiming control means so as to clear a load pulse generating means. CONSTITUTION:A 1st clock generating means 30 uses a coding rate set value and an error correction coding/decoding clock so as to generate the 1st clock having the same period as the data period and the retiming pulse to adjust the operation of the load pulse generating means 31 so that the change point of a load pulse comes in the nearly midpoint of adjacent change points of the 1st clock. Moreover, when a load pulse retiming control means 32 detects that the change point of the generated load pulse is at the outside of a prescribed range in a period of a timer pulse, the load pulse generating means 31 is reset by using the retiming control pulse sent therefrom to bring forcibly the change point of the load pulse to the midpoint region. Thus, the load pulse is generated at nearly accurate period.
申请公布号 JPS63204835(A) 申请公布日期 1988.08.24
申请号 JP19870036346 申请日期 1987.02.19
申请人 FUJITSU LTD 发明人 ITO ETSUKO;HAZAMA HISAMICHI;MIYAMOTO BUNICHI;UEDA HISAO;INOUE TAKESHI
分类号 H04L27/34;H03M13/00;H04L1/00;H04L27/00 主分类号 H04L27/34
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