发明名称 MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To improve the step coverage of an Al interconnection by forming a contact hole shaped to an interlayer film once and forming a hole in size larger than the contact hole and in depth of a third or two third of the thickness of the interlayer film to the contact hole. CONSTITUTION:An element such as an N-P-NTr, a MOSTr, etc., is shaped to the surface of an N-type epitaxial layer 2 formed onto a P-type silicon substrate 1. A PSG film 12 as an interlayer film is shaped through vapor growth, and the PSG film 12 is etched selectively through a photoetching method, thus forming a contact hole 13. A second contact hole 14 in a size larger than the previously shaped contact hole 13 and in depth of a third or two third of the thickness of the PSG film 12 is shaped through the photoetching method, and an electrode is formed. Accordingly, the step coverage of an Al interconnection is improved, and the versatility of a circuit design and a mask design at a time when two-layer interconnection structure is formed is enhanced.
申请公布号 JPS63202942(A) 申请公布日期 1988.08.22
申请号 JP19870036433 申请日期 1987.02.18
申请人 NEC YAMAGATA LTD 发明人 ADACHI KAZUO
分类号 H01L23/522;H01L21/768 主分类号 H01L23/522
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