| 摘要 |
PURPOSE:To make an address comparison by only one address comparator by providing a storage area for an address coincidence bit in an instruction pre- fetch buffer, and holding the result of the address comparison in said storage area when an instruction is fetched. CONSTITUTION:When a comparing circuit obtains the coincidence between addresses in a memory address register MAR and a comparison address register ACR, its signal is stored in an element M7 corresponding to the starting instruction pre-fetch buffer PFB7. Then, when the contents of the instruction pre-fetch buffer PFB7 are moved to a PFB6, the contents of an address coincidence bit storage element M7 are also moved to an M6, thus moving them successively up to a storage element M0. The starting address of the instruction is compared in mode 0, and when the element M0 is on, an address coincidence interruption signal is generated to drive an instruction execution unit. |
