发明名称 |
CLOCK GENERATING CIRCUIT FOR EXTRACTING DIGITAL DATA |
摘要 |
PURPOSE:To attain optimum clock extraction by selecting the relation of phase between an input digital data and a clock as pi/2. CONSTITUTION:A pulse with a prescribed width generated from the ries of an input digital data and a signal being 1/2 frequency division of an output of a VCO 11 are inputted to a 2nd comparator circuit 10 and synchronization is applied at a point of pi/2 for the data being an optimum extraction point. Thus, the phase synchronization of pi/2 is applied between a pulse generated at the rising/falling of the input digital data and the clock being an output of the VCO 11. Then an error voltage outputted from a 2nd comparator circuit 17 is fed to a control voltage for setting pulse width of a 1st monostable multivibrator 10 so as to bring the phase difference to be pi/2. Thus, the data and clock are synchronized by the relation of phase of pi/2 without fail to attain the optimum clock extraction. |
申请公布号 |
JPS63200641(A) |
申请公布日期 |
1988.08.18 |
申请号 |
JP19870033052 |
申请日期 |
1987.02.16 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
FUJIWARA MOTOKI |
分类号 |
H03L7/08;H04L7/02;H04L7/033 |
主分类号 |
H03L7/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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