发明名称 PSEUDO FAULT GENERATING SYSTEM FOR CACHE MEMORY DEVICE
摘要 PURPOSE:To produce a pseudo fault with a single pseudo fault designating signal by instructing the specific one of plural levels at which the pseudo fault occurs based on the pulse width. CONSTITUTION:When a pseudo fault is produced at level '0', '0' and '0' are set at a pseudo fault designating level register 7 and a pseudo fault indicating flag 6 is set at '1'. Thus the output of a comparator 10 is set at '1' and the clock of a machine advances by a step since the resetting conditions of the flag 6 are satisfied. Then the flag 6 is set at '0' and only an EIF 45 having level '0' is set at '1' to be processed as a parity error of level '0'. As a result, the pseudo faults of all levels can be produced just by supplying the information showing levels to the register 7.
申请公布号 JPS63200250(A) 申请公布日期 1988.08.18
申请号 JP19870031616 申请日期 1987.02.16
申请人 NEC CORP 发明人 HANEZAWA YASUSHI
分类号 G06F12/08 主分类号 G06F12/08
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