| 摘要 |
The present invention provides a parallel or "flash" analog-to-digital converter circuit (A) including a plurality of voltage comparators (20a - 20g) arranged in first and second sets (F and E) adapted for receiving separate analog input signals. A push-pull configuration is employed in providing the analog input signal to the comparators of the two sets. The analog inputs (22a - 22d) of the comparators (20a - 20d) in the first set are provided an input signal V1 and the analog inputs (22e - 22g) of the comparators (20e - 20g) in the second set are provided an input signal V2 of equal magnitude but opposite polarity. Different reference voltages are provided to the reference inputs (24a - 24g) of the comparators by a series-connected resistor network (H). Two encoders (I and J) and an adder (K) are used to detect the number of output signals from the comparators in a similar logic state and provide a digital binary output signal corresponding to the number of such outputs. The present invention can be implemented in an alternative embodiment (L) that includes a source (M) of constant voltage which offsets the amplitude of one of the input signals V1 or V2. This enables the use of a simplified resistor network (N) that provides reference voltages which can be applied to reference inputs of comparators in both sets. The present invention can also be implemented advantageously as an integrated circuit of compact layout that minimizes cross talk among signals flowing through the circuit and thereby enhances the precision thereof. |
