发明名称 DIGITAL SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To obtain a block free from a skew by reading out all signals at the time point when signals corresponding to respective tracks are matched. CONSTITUTION:Reproducing head outputs on respective tracks are demodulated into symbols and symbol clocks by demodulators 1-1-1-N and the symbol clocks are counted by counters 7-1-7-N and symbol counts are outputted. Synchronizing signals of respective tracks are inputted to a synchronizing group deciding circuit 9, a block signal is formed and a frame address is generated and a frame address is generated from a D-FF 8. These signals from respective tracks are inputted to a multiplexer 12, switched by a track counter 13 and the contents of respective tracks are successively read out and written in a memory 15. Since the signal processing circuit reads out the demodulated symbols successively after inputting all of them, a block free from a skew can be obtained.
申请公布号 JPS63195872(A) 申请公布日期 1988.08.12
申请号 JP19870027611 申请日期 1987.02.09
申请人 SHARP CORP 发明人 IWAKI TETSUO;YAMAWAKI CHIAKI
分类号 G11B20/10 主分类号 G11B20/10
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