| 摘要 |
PURPOSE:To easily realize a desired filter characteristic and to realize a circuit without necessitating adjustment, with high stability, and possible to be miniaturized, by processing all of the data in a digital way without using an analog filter. CONSTITUTION:The titled circuit is operated with a fast clock 104 after reading a timing clock 102 at a D-FF3 by the output of a fast clock generator 2. A fast counter 4 is reset by the start point of the output clock of the FF3, and counts an interpolation time by the clock 104. The output of the counter 4 is latched with a sample timing 103 at a latch circuit 105, and a coefficient corresponding to the interpolation time is outputted from a coefficient ROM6. The output is multiplied by the output of a corresponding shift register 1 at corresponding multipliers 7-1-7-L, and all of the multiplied results are added and outputted by an adder 8. Those outputs are possible to be connected to a communication system in an asynchronous system separated from a digital signal 101. When the signal 101 is the one of one bit, it is enough to prepare one ROM as a FIR type digital filter 9.
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