发明名称 AUTOMATISCH ABSTIMMBARER DETEKTOR FUER FREQUENZMODULIERTE SIGNALE
摘要 A FM detection system using a phase locked loop (PPL 20) and including: a wave shaping comparator (7) for accepting a signal VCO2 from a voltage controlled oscillator (4) which is 90 DEG out of phase with a control signal VCO1 from the voltage controlled oscillator (4), the comparator reshaping the signal to a square wave; an in-lock detector (8) for accepting the square wave and a frequency modulated input signal (VFM) to provide a sum frequency and a difference frequency; a low-pass filter (9) cutting off the sum frequency component, and filtering out the difference frequency signal when the PLL (20) is unlocked; a comparator (10) for comparing the output of the low-pass filter (9) with a reference voltage (VREF1), and providing a constant logic level when the PLL (20) is locked, or providing a clock pulse corresponding to the difference frequency when the PLL (20) is unlocked; a ripple counter (11) for counting the clock pulse and providing a binary signal output reflective of the count; a D/A converter (12) for accepting the binary output to provide an analogue current; and the oscillation frequency of the voltage controlled oscillator (4) being controlled in response to the output voltage from an amplifier (3) of PLL (20) and the output current of the D/A converter (12). A large detection output is attained in spite of a small loop gain.
申请公布号 DE3802524(A1) 申请公布日期 1988.08.11
申请号 DE19883802524 申请日期 1988.01.28
申请人 SAMSUNG SEMICONDUCTOR AND TELECOMMUNICATIONS CO., LTD., GUMI, KYUNGSANGBUK, KR 发明人 MIN, SUNG-KI, INCHON, KR;MYUNG, CHAN-KYU, SEOUL, KR;SHIN, KI-HO, WOOLSAN, KR
分类号 H03D3/02;H03B5/12;H03D3/24;H03D7/00;H03L7/06;H03L7/10;(IPC1-7):H03D3/24 主分类号 H03D3/02
代理机构 代理人
主权项
地址