发明名称 HIGH PERFORMANCE MICROPROCESSOR INTEGRATED CIRCUIT AND REFERENCE OF MEMORY
摘要 <p>A method and apparatus for prechecking (probing) the validity of an access request for writing result data to an external system prior to executing the instruction that generates the result is provided. This allows instruction execution to continue uninterrupted in the event that the write is allowed. The microprocessor's Address Unit issues a "probe" request to the Memory Management Unit (MMU) via an internal bus while saving the instruction's virtual address in a virtual address buffer local to the Address Unit. The MMU checks the validity of the "probe" request without converting the virtual address to a physical address and issues an access grant signal which is saved by the microprocessor's Execution Unit for subsequent use. The Execution Unit processes the data in parallel to the MMU checking the validity of the probe request. If the virtual address associated with the probe request resulted in an access grant signal, then the Execution Unit issues a write request while the virtual address previously stored in the Address Unit is sent to the MMU for translation to a physical address. Both the write data and the physical address are stored in a buffer in the microprocessor's Bus Interface Unit (BIU) for subsequent transfer to an external system. The data is then written to the external system at the physical address provided by the BIU.</p>
申请公布号 JPS63193230(A) 申请公布日期 1988.08.10
申请号 JP19880011834 申请日期 1988.01.21
申请人 NATL SEMICONDUCTOR CORP <NS> 发明人 DON ARUPAATO;GIJI BAROORU;MOTEI BETSUKU;JIIPU BAIKOUSUKI;DAN BAIRAN;ERIOTSUTO KOOEN;REBU EPUSUTAIN;NIZAN JIERAAMAN;YAIA HADESU;YOABU HORANDEERU;BENII KONSUTANCHIN;JIYONASAN RIBII;RUUBEN MARUKO;BENII MEITARU;YAAKOBU MIRUSUTAIN;AARON OSUTOREE;RAMI SABAN;ARON SHIYACHIYAMU;BOUZU SHIYAHAARU;YOMUUTOBU SHIDEI;YURI WAIZAA
分类号 G06F9/38;G06F12/08;G06F12/10;G06F15/78 主分类号 G06F9/38
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