发明名称 DATA TRANSFER BUFFER EQUIPMENT
摘要 PURPOSE:To speed up the effective transfer rate of data by segmenting and transmitting plural continuous data stored in a block buffer register in response to a request unit. CONSTITUTION:Plural continuous data received from an input/output processor 1 and stored in a buffer memory 32 are transferred all at once to a buffer register 31 via parallel processing and held there. When a transfer request is produced from an input/output device I/O3, data prefetched by the register 31 is swept out to the I/O3 for each unit. When the prefetched data is remaining in the register 31, said data are sequentially swept out. In this case, the data width is also changed. When all data are swept out of the register 31, a using request RQb given to the memory 32 is sent again to a control circuit 33. Hereafter, said transfer action is repeated. As a result, the processing capacity of the memory 32 is improved and the effective data transfer speed is increased.
申请公布号 JPS63192150(A) 申请公布日期 1988.08.09
申请号 JP19870024314 申请日期 1987.02.04
申请人 NEC CORP 发明人 OTANI AKIO
分类号 G06F13/28;G06F13/38 主分类号 G06F13/28
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