| 摘要 |
PURPOSE:To obtain an AD converter which operates blow 1.5 V by combining a differential amplifier which operates below 1.5 V, a latching comparator, and an encoder circuit and converting a digital output to a logical level for operation below 1.5 V. CONSTITUTION:A clock is a complementary clock, which has a 'High' level VCH and a, 'Low' level VCL. The VCL is only lower than the higher voltage between the voltages at input terminals VIN1 and VIN2 so as to places a switching TR Q5 in a cutoff state, and the VCL is only lower than the higher voltage between the voltages at output terminals OP1 and OP2 so as to place a switching TR Q6 in a cutoff state. Here, the OP1 and OP2 are provided with positive feedback in hold mode, so the higher voltage is nearly as high as a source voltage VCC. Here, the VCL is only set below the possible minimum value of the higher voltage between the voltages at the input terminals VIN1 and VIN2 at the same time.
|
