| 摘要 |
<p>1354563 Data processing; shifting network SANDERS ASSOCIATES Inc 18 June 1971 [18 June 1970] 28807/71 Headings G4A and G4C A digital data shifting network shifts data in positional increments of powers of 2, e.g. if data is to be shifted by nineteen positions it is shifted by 2<SP>4</SP>(16) positions in one clock cycle, 2<SP>1</SP>(2) positions in a second clock cycle and by 2‹(1) position in a third clock cycle. Data is entered in a N bit register 18A (e.g. 1024 bits) having N corresponding skew networks (described in detail, Fig. 3, not shown). Each skew network is connected to each register position a power of two away from it by Y leads, e.g. SN1 is connected to L2, L3, L5, L9, L17, L33 &c. The desired shaft is received from an instruction and the most significant bit of the shift causes one of the Y leads to be enabled thus causing the first and largest shift. The shifted data passes through unit 17 back to register 18A and the next most significant shift bit enables another of the Y leads. This continues until the desired shift is completed. The network is used in a parallel vertical processor (Fig. 1, not shown).</p> |
