发明名称 PACKAGE FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To reduce the attenuation and the delay of a high-frequency signal by a method wherein a terminating treatment of a high-frequency signal line is executed on a wiring pattern formed on the surface of a package so that an internal wiring part can be shortened. CONSTITUTION:A high-frequency signal which is input through an external lead 2 passes through a route of a metallized pattern 3 on the side face, an internal wiring part 4, a through hole 18, a turned-back internal wiring part 17, a metallized pattern 6, on the side face, for turned-back signal extraction use and a wiring pattern 1 in this order; it is absorbed by a terminating resistor mounted in a terminating-resistor mounting region 5 which is situated between the wiring pattern 1 and a wiring pattern 15. By this method, if the wiring pattern, which is connected to the internal wiring part inside the package or to the external lead at the package via the through hole or the metallized pattern on the side face at the package, is installed on the surface of the package, it is possible to mount the terminating resistor on the package itself and to terminate a high-frequency transmission line effectively just near the package.
申请公布号 JPS63188961(A) 申请公布日期 1988.08.04
申请号 JP19870020901 申请日期 1987.01.30
申请人 NEC CORP 发明人 OOISHI ATSUYA
分类号 H01L23/12;H01L23/04;H01L23/50;H03K19/00;H03K19/0175 主分类号 H01L23/12
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