发明名称 PLL CIRCUIT
摘要 PURPOSE:To stably operate a PLL circuit with a high frequency by modulating a signal with the frequency signal from the D/A converter, which performs D/A conversion of the output frequency from a digital waveform generating circuit, to generate an output frequency signal. CONSTITUTION:One part of the signal oscillated by the first highly stable oscillation source 11 is inputted to one multiplier 12, and another part is inputted to a multiplier 14 through a 90 deg. phase shifter 13, and outputs of multipliers 12 and 14 are subjected to subtraction by an adder 15. The frequency signal oscillated by an oscillation source 17 which is highly stable similarly to the oscillation source 11 is converted to frequency signals different in phase by 90 deg. by a logic circuit 18, and they are converted to analog signals by D/A converters 19 and 20 and are inputted as modulating signals to multipliers 12 and 14 through filters 21 and 22. Consequently, the frequency of an output Vout of the adder 15 can be changed in a wide range if the clock frequency of the oscillation source 17 is converted to another frequency by the logic circuit 18 in accordance with the output of a digital filter 4. Thus, a stable output signal is obtained because highly stable oscillation sources 11 and 17 are used.
申请公布号 JPS63187729(A) 申请公布日期 1988.08.03
申请号 JP19870017349 申请日期 1987.01.29
申请人 FUJITSU GENERAL LTD 发明人 OKADA KAZUO
分类号 H03L7/06 主分类号 H03L7/06
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