发明名称 |
Carry-save-adder three binary dividing apparatus |
摘要 |
A high-speed dividing apparatus includes first and second carry-save adders and a half carry-save adder and the outputs of the first carry-save adder are connected to the inputs of the second carry-save adder and half carry-save adder. The first carry-save adder is capable of carrying out either the addition or the subtraction of the divisor. The second carry-save adder is adapted to carry out the subtraction of a divisor, and the half carry-save adder the addition thereof. The first and second carry-save adders generate half-sums and half-carries, and the half carry-save adder generates a half-carry. A half-sum of the divisor addition is obtained by inverting the half-sum of the second carry-save adder by an inverter. A pair of half-sum and half-carry is supplied to each of carry look-ahead logics. A carry look-ahead logic is connected to each adder. A quotient determining logic is adapted to determine quotient bits in response to outputs from carry-save adder and half carry-save adder and carry look-ahead logics. A selector control logic controls a selector in accordance with the quotient such that one of the pairs of the half-sums and half-carries of the divisor addition and divisor subtraction, and either the divisor or its inversion are supplied to the first carry-save adder. An arbitrary number of stages can be arranged in a binary tree configuration in the same manner.
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申请公布号 |
US4761757(A) |
申请公布日期 |
1988.08.02 |
申请号 |
US19860818687 |
申请日期 |
1986.01.14 |
申请人 |
HITACHI, LTD. |
发明人 |
SAKAI, TATSUYA;ISHIKAWA, SAKOU |
分类号 |
G06F7/537;G06F7/508;G06F7/52;G06F7/535;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/537 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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