Data input/output device

摘要

The invention concerns a data input and output device with several I/O units (MT), at least one data I/O buffer memory (106a, 106b), to which at least two of the I/O units are assigned, several control units (100a, 100b), which are arranged between the I/O units and a CPU system (10) and are connected to the buffer memory, and a memory device (120), which is connected to the control units and stores necessary information from them to control the I/O units. If a first control unit (e.g. 100a) receives an I/O request for a first I/O unit from a CPU system (10), the data exchange between the first I/O unit (e.g. MT1) and the CPU system (10) takes place using the buffer memory (106a) which is assigned to the first I/O unit. If, during such a data exchange, a second control unit (e.g. 100b) receives from the CPU system (10) an I/O request for an I/O unit which shares the same buffer, the second control unit (e.g. 100b) does not use its own buffer memory (e.g. 106b), but activates its data transfer circuit for a data transfer to the first control unit (e.g. 100a), and thus carries out a further data exchange between the CPU system (10) and the identified I/O unit, by common use of the same buffer memory. The data exchange between the CPU system and the I/O units is by common ... Original abstract incomplete. <IMAGE>