发明名称 INPUT/OUTPUT TIMING GENERATION SYSTEM FOR PARTIAL IMAGE
摘要 PURPOSE:To speedily modify the timing of a processing-request for an input partial picture, an output partial picture, and a processor by modifying an address counter part with two parameters and shifting equivalently the coordinate origin of address generation to move the position of an input/output partial picture on the screen. CONSTITUTION:The address counter part 51 is constituted of registers 1, 2, counters 3, 4 to count relative addresses in the row-direction and the column- direction, buffer gates 5, 6 to read out the content in the registers 1, 2, a vertical synchronizing signal input terminal 11, a horizontal synchronizing signal input terminal 12, a clock signal input terminal 13, and a data input terminal 9. If values -Ny and -Nx are stored in the registers 1, 2, such input instruction signal and output instruction signal that an input partial picture and an output partial picture come in positions on the screen shifted from the positions in case the registers 1, 2 are both in '0' respectively by Ny downward and Nx to the right-hand side, are generated. Further, after the reading of the content in the registers 1, 2, prescribed shifting amounts - Ny and - Nx are added to the data then stored there again, hence relative movings for a length of Ny downward and Nx to the right can be attained.
申请公布号 JPS63182975(A) 申请公布日期 1988.07.28
申请号 JP19870014589 申请日期 1987.01.23
申请人 NEC CORP 发明人 TAMIYA ICHIRO
分类号 H04N5/262;G09G1/00;G09G5/14;G09G5/32;G09G5/36 主分类号 H04N5/262
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