| 摘要 |
PURPOSE:To realize both high-speed and flexible processing functions at a time by using the subtractors, multipliers, adders, a maximum/medium/minimum value detector, and a logical operation element. CONSTITUTION:The title circuit is provided with subtractors 7-9, multipliers 10-12, adders 20, 21 and 23, a maximum/medium/minimum value detector 24, and a logical computing element 25 and they are selected adaptively their functions via 1st, 2nd and 3rd selectors 13, 15-17 and 26 respectively. Especially the subtractors and multipliers can perform the parallel arithmetic operations of plural picture data. In other words, a 1st picture data (e.g., the picture data on the local areas of a picture to be processed) and the weighting data set previously are inputted in parallel to the subtractors and multipliers after the weighting data is selected by the 1st selector. Then the outputs subtractors are selected by the 2nd selector and the value obtained by subtracting the fixed value from the 1st picture data is inputted to the adder. Then the outputs of adders are selected by the 3rd selector for acquisition of the results of these additions.
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