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发明名称
Trigger re-synchronization circuit.
摘要
A trigger re-synchronization circuit providing reduced trigger gate jitter for use in a high speed display device such as an oscilloscope or digitizer. The trigger re-synchronization circuit is cascadable.
申请公布号
EP0276157(A2)
申请公布日期
1988.07.27
申请号
EP19880300493
申请日期
1988.01.21
申请人
TEKTRONIX, INC.
发明人
METZ, ARTHUR J.
分类号
G01R13/32;G01R13/34
主分类号
G01R13/32
代理机构
代理人
主权项
地址
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