发明名称 MOS static memory circuit
摘要 Voltage converters are arranged in units of columns in a memory device. Each voltage converter is connected to a column decoder. The column decoder receives a column address signal and supplies a column selection signal to the voltage converter. The voltage converters apply a ground level voltage to the source junctions of the drive transistor pairs of the memory cells of the selected columns, and a voltage higher than the ground level voltage to the source junctions of the drive transistor pairs of the memory cells of the nonselected columns so as to decrease power consumption in the nonselected columns as compared with that in the selected columns.
申请公布号 US4760562(A) 申请公布日期 1988.07.26
申请号 US19850800270 申请日期 1985.11.21
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 OHTANI, TAKAYUKI
分类号 G11C11/419;(IPC1-7):G11C13/00;G11C7/00 主分类号 G11C11/419
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