| 摘要 |
<p>PURPOSE:To secure synchronism, by dividing the frequency of a clock signal through plural microprocessors, comparing one of frequency-divided signal as a reference signal with others, and inhibiting clock input for signals with differences and making corrections. CONSTITUTION:A clock signal CK from an oscillator 3 is inputted to the normal and reverse input terminals of a main processor 1, which outputs a main frequency-divided signal Cm. When frequency-division outputs Cs and Cm of a slave processor 2 are both at a level ''0'', the output Ga of an ENR5 is at a level ''1'' and an FF6 latches it; when the signal CK rises, the FF6 is triggered and an AND gate 7 generates an output. A positive and a negative signal CK are inputted to the slave processor 2, which starts outputting a subordinate frequency- divided signal Cs; and the outputs Cm and Cs are out of phase with each other and the output Ga goes down to the level ''0'' to cut off the signals to the processor 2, so that the Cs is at the level ''0'' continuously. When the CK goes down to ''0'', the ENR5 generates the output again and the gate 7 outputs ''1''. At this time, the Cm and Cs are put in phase at the timing of the CK. Thus, the synchronism is secured.</p> |
