发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 <p>PURPOSE:To further access the specific number of memory cells in addition to the specific number of the memory cells by providing an address conversion circuit supplying bit line address data corresponding to the content of a mode switching signal to a multiplexer control circuit. CONSTITUTION:If the mode switching signal MS is a first content, the address conversion circuit 6 control in such a way that a bit line address data ADB controls a multiplexer, and the K number of memory cells H(i,1) among the (NXK) number of memory cells H(i,1)-H(i,NK) connected with a word line Wi in a memory cell array 1 are connected with the K number of data input output lines D1-Dk. Furthermore, if the signal MS is a second content, the circuit 6 controls data ADB in such a way that the signal MS controls the multiplexer 4 and a couple of memory cells except for Kpcs. in the (NXK) number of cells H(i,1)-H(1,NK) are connected with the word line Wi in the array 1.</p>
申请公布号 JPS63177391(A) 申请公布日期 1988.07.21
申请号 JP19870008656 申请日期 1987.01.17
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 SHIBATA SHINTARO;YANAKA KAZUHISA;HORIGUCHI MASATOSHI
分类号 G11C7/00;G06T1/60 主分类号 G11C7/00
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