| 摘要 |
PURPOSE:To improve the using efficiency of a bus by having such a structure where a processor can execute the internal bus cycles including a direct memory access cycle, a refresh cycle, etc. in a waiting mode for acquisition of using right for common bus. CONSTITUTION:A processor 2 produces direct memory access DMA request signals DMRQ1-n through an input/output controller 5 or a refresh request signal REFRQ through an internal memory 4 in a waiting mode for acquisition of using right for common bus. Then an internal bus control circuit 6 produces an internal bus use inhibiting signal to extend the waiting time of the processor 2 and at the same time floats a bus driver 3 to separate the processor 2 from an internal bus I-BUS. Thus the DMA or refresh cycle is started. In a non-waiting mode a holding request signal is sent to the processor 2 when signals DMARQ1-n and REFRQ are received. Then the processor 2 transmits a request signal, and the DMA or refresh cycles are started when the processor 2 is put under a holding state. |
