| 摘要 |
<p>A direct memory access (DMA) controlled system which performs DMA data transfer between a main memory (21), a cache memory (7), and disk memories (5,6) while exchanging DMA transfer requests and acknowledgements among disk control units (2,3), a memory-to-memory transfer control unit (13), and a common DMA control unit (12). The data transfer speed between the main memory (21) and cache memory (7) is variable according to the load condition of the DMA control unit (12) for the disk memories (5,6), enabling the transfer capability of the DMA control unit (12) to be kept at a fixed, continually high level.</p> |
