| 摘要 |
A CCD storage register for storing an area array of picture elements in a solid-state imager comprises a plurality of charge transfer channels in a parallel array. Charge transfer stages in those channels have corresponding charge storage sites facilitating charge transfer from each charge transfer stage to its corresponding charge storage site. Provisions are also made for charge transfer from each charge storage site back to its corresponding charge transfer stage or to a subsequent charge transfer stage. Such charge transfer schemes allows shift and add procedures to be carried forward in the CCD storage register. The shift and add capability allows time-delay-integration procedures and true line interlacing procedures, as examples, to be carried forward in the CCD storage register.
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