| 摘要 |
PURPOSE:To prevent occurrence of a latch-up phenomenon due to formation of a parasitic thyristor, by connecting sources of P channel and N channel transistors, which are formed on a substrate, with a power source and a ground, respectively, through resistances. CONSTITUTION:A resistance 2 is connected between a source 41 of a P channel MOS transistor 4 and a terminal 8 of a positive voltage power source. A resistance 3 is connected between a source 51 of an N channel MOS transistor 5 and a ground, and so a CMOS gate circuit with an input terminal 6 and an output terminal 7 is composed. When values of the resistances inserted between the sources of transistors and the power source terminals are set properly in this CMOS integrated circuit, conditions preventive of a latch-up phenomenon can be easily satisfied. |
