发明名称 FLOATING POINT ARITHMETIC UNIT
摘要 PURPOSE:To use an adder in common, and to use in common a mantissa shift for an arithmetic processing and a shifter for a normalizing processing, by executing an exchange of processing procedures of an absolute value conversion and normalizing, and a separation of an absolute value conversion processing by an exponent comparison result and a round-off processing. CONSTITUTION:In a procedure of a floating point arithmetic processing, in case when a relation of exponents e1, e2 of a floating point data is e1not equal to e2, it is necessary to shift mantissas f1, f2 to the right for the digit alignment, but in a large of small relation of the exponents e1, e2, a control can be executed so that a result of subtraction of the mantissas always becomes positive. Accordingly, an absolute value conversion processing 11 becomes unnecessary, but one bit of a result of addition and subtraction becomes '1' and a round-off processing 13 is necessary. Accordingly, as shown by a but 16, the processing 11 and the processing 13 can be executed exclusively by a relation of the exponents e1, e2. The processing procedures of the normalizing processing 12 and the processing 11 can be exchanged, and the processing procedure by the bus 15 and 16 can be executed. In such a way, the processing 11 and the processing 13 and be executed exclusively, both the arimetic operations are operations using an adder, and the adder required therefor can be used in common.
申请公布号 JPS63167930(A) 申请公布日期 1988.07.12
申请号 JP19860311024 申请日期 1986.12.29
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 UEDA KATSUHIKO
分类号 G06F7/00;G06F7/38;G06F7/485;G06F7/50;G06F7/76 主分类号 G06F7/00
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