| 摘要 |
PURPOSE:To contrive a speedup and a reduction in power consumption at low temperature by a method wherein SiN-MOS and P-MOS transistors, each having a source and a drain which are formed by Schottky junction with a specified metal, are provided. CONSTITUTION:A p-type well region 2, a field oxide film 3, a gate oxide film 4, an n<+> poly Si film 5 and a p<+> poly Si film 6 are formed in and on an n-type Si substrate 1. Then, the surface is oxidized to form oxide films 7 and source and drain regions 8 which are used as a source and a drain. An etching is performed by the amount of the thickness of the oxide films on the regions 8 and the substrate 1 is exposed on the regions 8. An Hf (hafnium) layer 9 is deposited on the whole surface, resist patterns 10 are each formed on Schottky barrier forming regions and after part of the Hf layer 9 is removed, the resist patterns 10 are removed to form Schottky electrodes 11 consisting of the Hf layer 9 and a CMOS device is obtained. |
